Publications Number 6500-10A
MCS6500
MICROCOMPUTER FAMILY
PROGRAMMING MANUAL
JANUARY 1976
The information in this manual has been reviewed and is believed to be entirely reliable. However,
no responsibility is assumed for inaccuracies. The material in this manual is for informational
purposes only and is subject to change without notice.
Second Edition
© MOS TECHNOLOGY, INC. 1976
"All Rights Reserved"
MOS TECHNOLOGY, INC.
950 Rittenhouse Road
Norristown, PA 19401
Revision A
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTORY REMARKS
1.0 Manual Introduction . . . . . . . . . . . . . . . . . . . . .1
1.1 Microprocessor Architecture . . . . . . . . . . . . . . . . .2
CHAPTER 2 THE DATA BUS, ACCUMULATOR AND ARITHMETIC UNIT
2.0 The Data Bus. . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 The Accumulator . . . . . . . . . . . . . . . . . . . . . . .4
2.1.1 LDA--Load Accumulator with Memory . . . . . . . . . . . . .4
2.1.2 STA--Store Accumulator in Memory. . . . . . . . . . . . . .5
2.2 The Arithmetic Unit . . . . . . . . . . . . . . . . . . . . .6
2.2.1 ADC--Add Memory with Carry to Accumulator . . . . . . . . .7
2.2.1.0 Multiple Precision Addition . . . . . . . . . . . . . . .8
2.2.1.1 Signed Arithmetic . . . . . . . . . . . . . . . . . . . 10
2.2.1.2 Decimal Addition. . . . . . . . . . . . . . . . . . . . 13
2.2.1.3 Add Summary . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 SBC--Subtract Memory from Accumulator with Borrow . . . . 14
2.2.2.0 Multiple Precision Subtraction. . . . . . . . . . . . . 16
2.2.2.1 Signed Arithmetic . . . . . . . . . . . . . . . . . . . 18
2.2.2.2 Decimal Subtract. . . . . . . . . . . . . . . . . . . . 19
2.2.3 Carry and Overfiow During Arithmetic Operations . . . . . 20
2.2.4 Logical Operands. . . . . . . . . . . . . . . . . . . . . 20
2.2.4.1 AND--"AND" Memory with Accumulator. . . . . . . . . . . 20
2.2.4.2 ORA--"OR" Memory with Accumulator . . . . . . . . . . . 21
2.2.4.3 EOR--"Exclusive OR" Memory with Accumulator . . . . . . 21
CHAPTER 3 CONCEPTS OF FLAGS AND STATUS REGISTER
3.0 Carry Flag (C). . . . . . . . . . . . . . . . . . . . . . . 24
3.0.1 SEC--Set Carry Flag . . . . . . . . . . . . . . . . . . . 24
3.0.2 CLC--Clear Carry Flag . . . . . . . . . . . . . . . . . . 25
3.1 Zero Flag (Z) . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Interrupt Disable (I) . . . . . . . . . . . . . . . . . . . 25
3.2.1 SET--Set Interrupt Disable. . . . . . . . . . . . . . . . 26
3.2.2 CLI--Clear Interrupt Disable. . . . . . . . . . . . . . . 26
ii
3.3 Decimal Node Flag (D) . . . . . . . . . . . . . . . . . . . 26
3.3.1 SED--Set Decimal Mode . . . . . . . . . . . . . . . . . . 26
3.3.2 CLD--Clear Decimal Node . . . . . . . . . . . . . . . . . 27
3.4 Break Command (B) . . . . . . . . . . . . . . . . . . . . . 27
3.5 Expansion Bit . . . . . . . . . . . . . . . . . . . . . . . 27
3.6 Overflow (V). . . . . . . . . . . . . . . . . . . . . . . . 27
3.6.1 CLV--Clear Overflow Flag. . . . . . . . . . . . . . . . . 28
3.6.2 Determination of Overflow . . . . . . . . . . . . . . . . 28
3.7 Negative Flag (N) . . . . . . . . . . . . . . . . . . . . . 29
3.8 Flag Summary. . . . . . . . . . . . . . . . . . . . . . . . 30
CHAPTER 4 TEST, BRANCH AND JUMP INSTRUCTIONS
4.0 Concepts of Program Sequence. . . . . . . . . . . . . . . . 31
4.0.1 Use of Program Counter to Fetch an Instruction. . . . . . 33
4.0.2 JMP--Jump to New Location . . . . . . . . . . . . . . . . 36
4.1 Branching . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 Basic Concept of Relative Addressing. . . . . . . . . . . 38
4.1.2 Branch Instructions . . . . . . . . . . . . . . . . . . . 40
4.1.2.1 BMI--Branch on Result Minus . . . . . . . . . . . . . . 40
4.1.2.2 BPL--Branch on Result Plus. . . . . . . . . . . . . . . 40
4.1.2.3 BCC--Branch on Carry Clear. . . . . . . . . . . . . . . 40
4.1.2.4 BCS--Branch on Carry Set. . . . . . . . . . . . . . . . 40
4.1.2.5 BEQ--Branch on Result Zero. . . . . . . . . . . . . . . 41
4.1.2.6 BNE--Branch on Result Not Zero. . . . . . . . . . . . . 41
4.1.2.7 BVS--Branch on Overflow Set . . . . . . . . . . . . . . 41
4.1.2.8 BVC--Branch on Overflow Clear . . . . . . . . . . . . . 41
4.1.3 Branch Summary. . . . . . . . . . . . . . . . . . . . . . 42
4.1.4 Solution to Branch Out of Range . . . . . . . . . . . . . 42
4.2 Test Instructions . . . . . . . . . . . . . . . . . . . . . 45
4.2.1 CMP--Compare Memory and Accumulator . . . . . . . . . . . 45
4.2.2 Bit Testing . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.2.1 BIT--Test Bits in Memory with Accumulator . . . . . . . 47
CHAPTER 5 NON-INDEXING ADDRESSING TECHNIQUES
5.0 Addressing Techniques . . . . . . . . . . . . . . . . . . . 50
5.1 Concepts of Pipelining and Program Sequence . . . . . . . . 52
5.2 Memory Utilization. . . . . . . . . . . . . . . . . . . . . 56
5.2.1 I/O Control . . . . . . . . . . . . . . . . . . . . . . . 56
5.2.2 Memory Allocation . . . . . . . . . . . . . . . . . . . . 57
5.3 Implied Addressing. . . . . . . . . . . . . . . . . . . . . 57
5.4 Immediate Addressing . . . . . . . . . . . . . . . . . . . 59
5.5 Absolute Addressing . . . . . . . . . . . . . . . . . . . . 59
5.6 Zero Page Addressing. . . . . . . . . . . . . . . . . . . . 61
5.7 Relative Addressing . . . . . . . . . . . . . . . . . . . . 63
iii
CHAPTER 6 INDEX REGISTERS AND INDEX ADDRESSING CONCEPTS
6.0 General Concept of Indexing . . . . . . . . . . . . . . . . 69
6.1 Absolute Indexed. . . . . . . . . . . . . . . . . . . . . . 79
6.2 Zero Page Indexed . . . . . . . . . . . . . . . . . . . . . 81
6.3 Indirect Addressing . . . . . . . . . . . . . . . . . . . . 83
6.4 Indexed Indirect Addressing . . . . . . . . . . . . . . . . 85
6.5 Indirect Indexed Addressing . . . . . . . . . . . . . . . . 87
6.6 Indirect Absolute . . . . . . . . . . . . . . . . . . . . . 92
6.7 Application of Indexes. . . . . . . . . . . . . . . . . . . 92
CHAPTER 7 INDEX REGISTER INSTRUCTIONS
7.0 LDX--Load Index Register X from Memory. . . . . . . . . . . 96
7.1 LDY--Load Index Register Y from Memory. . . . . . . . . . . 96
7.2 STX--Store Index Register X in Memory . . . . . . . . . . . 97
7.3 STY--Store Index Register Y in Memory . . . . . . . . . . . 97
7.4 INX--Increment Index Register X by One. . . . . . . . . . . 97
7.5 INY--Increment Index Register Y by One. . . . . . . . . . . 97
7.6 DEX--Decrement Index Register X by One . . . . . . . . . . 98
7.7 DEY--Decrement Index Register Y by One . . . . . . . . . . 98
7.8 CPX--Compare Index Register X to Memory . . . . . . . . . . 99
7.9 CPY--Compare Index Register Y to Memory . . . . . . . . . . 99
7.10 Transfers Between the Index Registers and Accumulator. . .100
7.11 TAX--Transfer Accumulator to Index X . . . . . . . . . . .100
7.12 TXA--Transfer Index X to Accumulator . . . . . . . . . . .100
7.13 TAY--Transfer Accumulator to Index Y . . . . . . . . . . .101
7.14 TYA--Transfer Index Y to Accumulator . . . . . . . . . . .101
7.15 Summary of Index Register Applications and Manipulations .102
CHAPTER 8 STACK PROCESSING
8.0 Introduction to Stack and to Push Down Stack Concept. . . .103
8.1 JSR--Jump to Subroutine . . . . . . . . . . . . . . . . . .104
8.2 RTS--Return from Subroutine . . . . . . . . . . . . . . . .108
8.3 Implementation of Stack in MC56501 Through MC56505. . . . .112
8.3.1 Summary of Stack Implementation . . . . . . . . . . . . .115
8.4 Use of the Stack by the Programmer . . . . . . . . . . . .116
8.5 PHA--Push Accumulator on Stack. . . . . . . . . . . . . . .117
8.6 PLA--Pull Accumulator from Stack. . . . . . . . . . . . . .118
8.7 Use of Pushes and Pulls to Communicate Variables Between. .
Subroutine Operations. . . . . . . . . . . . . . . . . .119
8.8 TXS--Transfer Index X to Stack Pointer. . . . . . . . . . .120
8.9 TSX--Transfer Stack Pointer to Index X. . . . . . . . . . .122
8.10 Saving of the Processor Status Pointer . . . . . . . . . .122
8.11 PHP--Push Processor Status on Stack. . . . . . . . . . . .122
8.12 PLP--Pull Processor Status from Stack. . . . . . . . . . .123
8.13 Summary on the Stack . . . . . . . . . . . . . . . . . . .123
iv
CHAPTER 9 RESET AND INTERRUPT CONSIDERATIONS
9.0 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.1 Reset or Restart. . . . . . . . . . . . . . . . . . . . . .125
9.2 Start Function. . . . . . . . . . . . . . . . . . . . . . .126
9.3 Programmer Considerations for Initialization. . . . . . . .127
9.4 Restart . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.5 Interrupt Considerations. . . . . . . . . . . . . . . . . .129
9.6 RTI--Return from Interrupt. . . . . . . . . . . . . . . . .132
9.7 Software Polling for Interrupt Causes . . . . . . . . . . .137
9.8 Fully Vectored Interrupts . . . . . . . . . . . . . . . . .140
9.8.1 JMP Indirect. . . . . . . . . . . . . . . . . . . . . . .141
9.9 Interrupt Summary . . . . . . . . . . . . . . . . . . . . .142
9.10 Non-Maskable Interrupt . . . . . . . . . . . . . . . . . .142
9.11 BRK--Break Command . . . . . . . . . . . . . . . . . . . .144
9.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . .146
CHAPTER 10 SHIFT AND MEMORY MODIFY INSTRUCTIONS
10.0 Definition of Shift and Rotate . . . . . . . . . . . . . .147
10.1 LSR--Logical Shift Right . . . . . . . . . . . . . . . . .148
10.2 ASL--Arithmetic Shift Left . . . . . . . . . . . . . . . .149
10.3 ROL--Rotate Left . . . . . . . . . . . . . . . . . . . . .149
10.4 ROR--Rotate Right. . . . . . . . . . . . . . . . . . . . .150
10.5 Accumulator Mode Addressing. . . . . . . . . . . . . . . .150
10.6 Read/Modify/Write Instructions . . . . . . . . . . . . . .151
10.7 INC--Increment Memory by One . . . . . . . . . . . . . . .154
10.8 DEC--Decrement Memory by One . . . . . . . . . . . . . . .155
10.9 General Note on Read/Modify/write Instructions . . . . . .155
CHAPTER 11 PERIPHERAL PROGRAMMING
11.0 Review of MC56520 for I/O Operations . . . . . . . . . . .156
11.1 MC56520 Interrupt Control. . . . . . . . . . . . . . . . .158
11.2 Implementation Tricks for Use of the MC56520 Peripheral. .
Interface Devices . . . . . . . . . . . . . . . . . . .161
11.2.1 Shortcut Polling Sequences . . . . . . . . . . . . . . .161
11.2.2 Bit Organization on MCS6520s . . . . . . . . . . . . . .162
11.2.3 Use of READ/MODIFY/WRITE Instruction for Keyboard. . . .
Encoding. . . . . . . . . . . . . . . . . . . . . . .163
11.3 MC56530 Programming. . . . . . . . . . . . . . . . . . . .166
11.3.1 Reading of the Counter Register. . . . . . . . . . . . .166
11.4 How to Organize to Implement Coding. . . . . . . . . . . .166
11.4.1 Label Standards. . . . . . . . . . . . . . . . . . . . .168
11.5 Comprehensive I/O Program. . . . . . . . . . . . . . . . .170
v
APPENDICES
A. Instruction List, Alphabetic by Mnemonic, Definition . .
of Instruction Groups. . . . . . . . . . . . . . . . .A-1
MCS6505 Microprocessor Instruction Set
Alphabetic Sequence. . . . . . . . . . . . . . . . . .A-2
A.1 Introduction. . . . . . . . . . . . . . . . . . . . . . .A-3
A.2 Group One Instructions . . . . . . . . . . . . . . . . .A-3
A.3 Group Two Instructions . . . . . . . . . . . . . . . . .A-4
A.4 Group Three Instructions . . . . . . . . . . . . . . . .A-5
B. Instruction List, Alphabetic by Mnemonic, with OP CODEs,
Execution Cycles and Memory Requirements . . . . . B-1
C. Instruction Addressing Modes and Related Execution Times C-1
D. Operation Code Instruction Listing Hexadecinal Sequence. D-1
E. Summary of Addressing Modes
E.1 Implied Addressing. . . . . . . . . . . . . . . . . .E-2
E.2 Immediate Addressing. . . . . . . . . . . . . . . . .E-3
E.3 Absolute Addressing . . . . . . . . . . . . . . . . .E-3
E.4 Zero Page Addressing. . . . . . . . . . . . . . . . .E-4
E.5 Relative Addressing . . . . . . . . . . . . . . . . .E-4
E.6 Absolute Indexed Addressing . . . . . . . . . . . . .E-5
E.7 Zero Page Indexed Addressing. . . . . . . . . . . . .E-6
E.8 Indexed Indirect Addressing . . . . . . . . . . . . .E-7
E.9 Indirect Indexed Addressing . . . . . . . . . . . . .E-8
F. MCS65OX Programming Model . . . . . . . . . . . . . . . .F-1
G. Discussion--Indirect Addressing . . . . . . . . . . . . .G-1
H. Review of Binary and Binary Coded Decimal Arithmetic. . .H-1
vi
LIST OF EXAMPLES
CHAPTER 2 THE DATA BUS, ACCUMULATOR AND ARITHMETIC UNIT
2.1 Add 2 Numbers with Carry; No Carry Generation . . . . . . .7
2.2 Add 2 Numbers with Carry; Carry Generation. . . . . . . . .8
2.3 Adding Two 16-Bit Numbers . . . . . . . . . . . . . . . . .9
2.4 Add Two 16-Bit Numbers, No Carry from Low Order Add . . . .9
2.5 Add Two 16-Bit Numbers, with Carry from Low Order Add . . 10
2.6 Add 2 Positive Numbers with No Overflow . . . . . . . . . 11
2.7 Add 2 Positive Numbers with Overflow. . . . . . . . . . . 12
2.8 Add Positive and Negative Number with Positive Result . . 12
2.9 Add Positive and Negative Number with Negative Result . . 12
2.10 Add 2 Negative Numbers without Overflow . . . . . . . . . 12
2.11 Add 2 Negative Numbers with Overflow. . . . . . . . . . . 13
2.12 Decimal Addition. . . . . . . . . . . . . . . . . . . . . 13
2.13 Subtract 2 Numbers with Borrow; Positive Result . . . . . 15
2.14 Subtract 2 Numbers with Borrow; Negative Result . . . . . 16
2.15 Subtracting Two 16-Bit Numbers. . . . . . . . . . . . . . 16
2.16 Subtract in Double Precision Format; Positive Result. . . 17
2.17 Subtract in Double Precision Format; Negative Result. . . 18
2.18 Decimal Subtraction . . . . . . . . . . . . . . . . . . . 19
2.19 Clearing a Bit with "AND" . . . . . . . . . . . . . . . . 21
2.20 Setting a Bit with "OR" . . . . . . . . . . . . . . . . . 21
2.21 Complementing a Byte with "EOR" . . . . . . . . . . . . .
CHAPTER 4 TEST, BRANCH AND JUMP INSTRUCTIONS
4.1 Accessing Instructions with the P-Counter Value . . . . . 33
4.2 Accessing Data Addressing with P-Counter Value. . . . . . 34
4.3 Use of JMP Instruction. . . . . . . . . . . . . . . . . . 36
4.4 Illustration of "Branch on Carry Set" . . . . . . . . . . 38
4.5 Sequencing Two Branch Instructions. . . . . . . . . . . . 39
4.6 Use of JMP to Branch Out of Range . . . . . . . . . . . . 43
4.7 Using the CMP Instruction . . . . . . . . . . . . . . . . 46
4.8 Sample Program Using the BIT Test . . . . . . . . . . . . 48
vii
CHAPTER 5 NON-INDEXING ADDRESSING TECHNIQUES
5.1 Using Absolute Addressing . . . . . . . . . . . . . . . . 51
5.2 Demonstration of "Pipelining" Effect. . . . . . . . . . . 54
5.3 Illustration of Implied Addressing. . . . . . . . . . . . 58
5.4 Illustration of Immediate Addressing. . . . . . . . . . . 59
5.5 Illustration of Absolute Addressing . . . . . . . . . . . 60
5.6 Illustration of Zero Page Addressing. . . . . . . . . . . 62
5.7 Illustration of Relative Addressing; Branch Not Taken . . 63
5.8 Illustration of Relative Addressing; Branch Positive
Taken, No Crossing of Page Boundaries. . . . . . . . . 64
5.9 Illustration of Relative Addressing; Branch Negative
Taken, Crossing of Page Boundaries . . . . . . . . . . 65
CHAPTER 8 STACK PROCESSING
8.1 Basic Stack Map for 3-Deep JMP to Subroutine. . . . . . .104
8.2 Basic Stack Operation . . . . . . . . . . . . . . . . . .105
8.3 Illustration of JSR Instruction . . . . . . . . . . . . .106
8.4 Illustration of RTS Instruction . . . . . . . . . . . . .109
8.5 Memory Map for RTS Instruction. . . . . . . . . . . . . .111
8.6 Expansion of RTS Memory Map . . . . . . . . . . . . . . .111
8.7 Call-a-Move Subroutine Using Preassigned Memory Locations116
8.8 Operation of PHA, Assuming Stack at 01FF. . . . . . . . .118
8.9 Operation of PLA Stack from Example 8.8 . . . . . . . . .119
8.10 Call-a-Move Subroutine Using the Stack to Communicate . .119
8.11 Jump to Subroutine (JSR) Followed by Parameters . . . . .121
viii
CHAPTER 9 RESET AND INTERRUPT CONSIDERATIONS
9.1 Illustration of Start Cycle . . . . . . . . . . . . . . .127
9.2 Interrupt Sequence. . . . . . . . . . . . . . . . . . . .131
9.3 Return from Interrupt . . . . . . . . . . . . . . . . . .133
9.4 Illustration of Save and Restore for Interrupts . . . . .133
9.5 Interrupt Polling . . . . . . . . . . . . . . . . . . . .137
9.6 Illustration of JMP Indirect. . . . . . . . . . . . . . .141
9.7 Break-Interrupt Processing. . . . . . . . . . . . . . . .145
9.8 Patching with a Break Utilizing PROMs . . . . . . . . . .146
CHAPTER 10 SHIFT AND MEMORY MODIFY INSTRUCTIONS
10.1 General Shift and Rotate. . . . . . . . . . . . . . . . .147
10.2 Rotate Accumulator Left . . . . . . . . . . . . . . . . .150
10.3 Rotate Memory Left Absolute,X . . . . . . . . . . . . . .151
10.4 Move a New BCD Number into Field. . . . . . . . . . . . .154
CHAPTER 11 PERIPHERAL PROGRAMMING
11.1 The MC56520 Register Map. . . . . . . . . . . . . . . . .156
11.2 General PIA Initialization. . . . . . . . . . . . . . . .157
11.3 Interrupt Mode Setup. . . . . . . . . . . . . . . . . . .159
11.4 CA2; CB2 Output Control . . . . . . . . . . . . . . . . .159
11.5 Routine to Change CB1 or CB2 Using Bit 3 Control . . . .160
11.6 Polling the MC56520. . . . . . . . . . . . . . . . . . .161
11.7 Coding for Strobing an 8 x 8 Keyboard . . . . . . . . . .164
11.8 Polling for Active Signal . . . . . . . . . . . . . . . .172
IX
LIST OF FIGURES
CHAPTER 2 THE DATA BUS, ACCUMULATOR AND ARITHMETIC UNIT
2.1 Partial Block Diagram of MCS65OX . . . . . . . . . . . . . 3
2.2 Partial Block Diagram Including Arithmetic Logic Unit
of MCS650X. . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Byte Orientation with Sign Position. . . . . . . . . . . .11
CHAPTER 3 CONCEPTS OF FLAGS AND STATUS REGISTER
3.1 Partial Block Diagram of MCS65OX Including P-Register. . .23
3.2 Processor Status Register, "P" . . . . . . . . . . . . . .24
CHAPTER 4 TEST, BRANCH AND JUMP INSTRUCTIONS
4.1 Partial Block Diagram of MC5650X Including Program
Counter and Internal Address Bus. . . . . . . . . . . .31
4.2 Use of Conditional Test. . . . . . . . . . . . . . . . . .37
CHAPTER 5 NON-INDEXING ADDRESSING TECHNIQUES
5.1 Address Bus and Relation to Memory Field . . . . . . . . .54
5.2 Example of Timing--MC5650x Family. . . . . . . . . . . . .55
CHAPTER 6 INDEX REGISTERS AND INDEX ADDRESSING CONCEPTS
6.1 Moving Five Bytes of Data with Loop. . . . . . . . . . . .72
6.2 Moving Five Bytes of Data with Counter . . . . . . . . . .75
6.3 Partial Block Diagram of MCS65OX Including Index Register.78
6.4 Indirect Addressing--Pictorial Drawing . . . . . . . . . .84
6.5 Indexed Indirect Addressing. . . . . . . . . . . . . . . .85
6.6 Indirect Indexed Addressing. . . . . . . . . . . . . . . .87
CHAPTER 8 STACK PROCESSING
8.1 Partial Block Diagram of MC5650X Including Stack
Pointer, S. . . . . . . . . . . . . . . . . . . . . . 113
CHAPTER 10 SHIFT AND MEMORY MODIFY INSTRUCTIONS
10.1 Flow Chart for Moving in a New BCD Number. . . . . . . . 153
CHAPTER 11 PERIPHERAL PROGRAMMING
11.1 Keyboard Encoding Matrix Program . . . . . . . . . . . . 163
11.2 Keyboard Strobe Sequence . . . . . . . . . . . . . . . . 165
11.3 Program Flow-Polling for Active Signal . . . . . . . . . 171
1.0 MANUAL INTRODUCTION
Welcome to the MCS650X product family. This manual is designed to
work in conjunction with the Hardware Manual which describes the basic
hardware considerations when using the MOS Technology, Inc. microcomputer
family.
Before reading this manual, it is suggested that the reader acquaint
himself with the Hardware Manual in order to understand the components
available in this system, how these components are interconnected, and
their basic architecture. Developed in this manual is the concept of
microprocessor internal architecture and how it is used, with attention
given to input/output considerations. Familiarity with the hardware will
facilitate easier understanding of these important concepts.
In order to best serve the total customer base, this manual is written
in two levels. The first is a very basic introduction to the MCS650X fam-
ily, and the second level is for the user who has to refer to the manual
on more than an occasional basis and who wants to rapidly scan and find
specific sections. For the user who is quite familiar with programming
and the MCS650X instruction set, the appendices are the best reference in
the sense that all the data which is discussed in detail in the manual is
summarized in a series of tables for convenience.
It is recommended that the user who is an experienced programmer and
familiar with microprocessors still take the time to read through the
manual in detail. Some of the architectural concepts are different from
those found in second generation machines and this manual instructs the
user how to optimize the utilization of the microprocessor while providing
an introduction of its basic concepts.
1
Criticism of this manual is welcomed at all times. Of particular
interest are cases where one could not, by use of the index and appendix,
rapidly find the answer to a question which developed in the course of
designing a microprocessor system. Welcomed are any comments which will
enhance the content and format of this manual in future editions or adden-
dums.
1.1 MICROPROCESSOR ARCHITECTURE
The MCS6501, MCS6502, MCS6503, MCS6504, and MCS6505 are all 8-bit
microprocessors. That means that 8 bits of data are transferred or oper-
ated upon during each instruction cycle or operation cycle.
All devices in the MCS650X family operate on data 8 bits at a time,
although some of the operations will look like serial or 16-bit wide oper-
ations. In a future section, discussed will be the use of sequential
operations on an 8-bit basis and how one can accomplish 16-bit effective
operands and addressing.
The computer industry, for some time, has been treating 8-bit combina-
tions of data by a term known as a 1'byte." In many large computers which
operate simultaneously on multiple bytes of data, the number of bytes which
are transferred and operated on by the machine in parallel are called a
"word." Because these microprocessors are 8-bit microprocessors, the words
and bytes are of equal length. Therefore, for convenience through the dis-
cussion of the basic 8-bit processors, "byte" and "word" will be used
synonymously although in some of the expanded versions there will exist a
16-bit word composed of two 8-bit bytes.
2.0 THE DATA BUS
Although most of the following discussion will consider how one
operates with a general purpose register called the accumulator, it must
be understood that data has to transfer between the accumulator and out-
side sources by means of passing through the microprocessor to 8 lines
called the data bus. The outside sources include the program which con-
trols the microprocessor, the memory which will be used as interim stor-
age for internal registers when they are to be used in a current opera-
tion, and the actual communications to the world through input/output
ports. Later in this document performance of transfers to and from each
of these devices will be discussed. However, at present, discussion
will center on the microprocessor itself.
Partial Block Diagram of MCS650X
FIGURE 2.1
The only operation of the data bus is to transfer data between mem-
ory and the processor's internal registers such as the accumulator. Fig-
ure 2.1 displays the basic communication between the accumulator, A, and
the memory, M, through the use of 8 bi-directional data lines called the
data bus.
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2.1 THE ACCUMULATOR
The accumulator is a register in which data is kept on which opera-
tions are performed. All operations between memory locations must be
communicated through the accumulator or one of the auxiliary index reg-
isters. The accumulator is used as a temporary storage in moving data
from one memory location to another. Therefore, the first use for the
accumulator (A) is just in transferring data from memory to the accumu-
lator or from the accumulator to memory One can bring data into the
accumulator, perform operations such as AND/OR on it, test the results
of those operations, set new bits into it, or transfer it back out to
the outside world. It serves as an interim storage for a series of oper-
actions such as adding 2 values together; where one of them is loaded into
the accumulator, the second one added to it, and the results stored in
the accumulator. The accumulator really acts as two functions: 1) It
is one of the primary storage points for the machine; 2) It is the point
at which intermediate results are normally stored.
2.1.1 LDA--Load Accumulator with Memory
When instruction LDA is executed by the microprocessor, data
is transferred from memory to the accumulator and stored in the
accumulator.
Rather than continuing to give a word picture of the opera-
tion, introduced will be the symbolic representation N + A, where
the arrow means "transfer to." Therefore the LDA instruction sym-
bolic representation is read, "memory transferred to the accumulator."
LDA affects the contents of the accumulator, does not affect
the carry or overflow flags; sets the zero flag if the accumulator
is zero as a result of the LDA, otherwise resets the zero flag;
sets the negative flag if bit 7 of the accumulator is a 1, other-
wise resets the negative flag.
Although yet to be developed is the concept of addressing
modes, for reference purpose, LDA is a "Group One" instruction and
has all of the major addressing nodes of the machine available to
it as stated in Appendix A. These addressing modes include Immed-
iate; Absolute; Zero Page; Absolute,X; Absolute,Y; Zero Page,X;
Indexed Indirect; and Indirect Indexed.
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2.1.2 STA--Store Accumulator in Memory
This instruction transfers the contents of the accumulator to
memory.
The symbolic representation for this instruction is A -> M.
This instruction affects none of the flags in the processor
status register and does not affect the accumulator.
It is a "Group One" instruction and has the following address-
ing modes available to it: Absolute; Zero Page; Absolute,X; Abso-
lute,Y; Zero Page,X; Indexed Indirect; and Indirect Indexed.
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2.2 THE ARITHMETIC UNIT
One of the functions to be expected from any computer is the ability
to compute or perform arithmetic operations. Even in a simple control
problem, one often finds it useful to add 2 numbers in order to determine
that a value has been reached, or subtract 2 numbers to calculate a new
value which must be obtained. In addition, many problems involve some
rudimentary form of decimal or binary arithmetic; certainly many applica-
tions of the microprocessor will involve both. The MCS650X has an 8-bit
arithmetic unit which interfaces to the accumulator as shown in Figure 2.2.
Partial Block Diagram including Arithmetic Logic Unit of MCS650X
FIGURE 2.2
The arithmetic unit is composed of several major parts. The most
important of these is the circuitry necessary to perform a two's comple-
ment add of 8-bit parallel values and generate an 8 parallel bit binary
result plus a carry. A review of binary and binary coded decimal (BCD)
arithmetic is presented in Appendix H. However, a quick review of the
concept of "carry" is in order. The largest range than can be repre-
sented in an 8-bit number is 256 with values ranging between 0 and 255.
If we add any 2 numbers which result in a sum which is greater than 255,
we represent the result with a ninth bit plus the 8 bits of the excess
over 255. The ninth bit is called "carry."
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2.2.1 ADC--Add Memory to Accumulator with Carry
This instruction adds the value of memory and carry from the
previous operation to the value of the accumulator and stores the
result in the accumulator.
The symbolic representation for this instruction is
A + M + C -> A.
This instruction affects the accumulator; sets the carry flag
when the sum of a binary add exceeds 255 or when the sum of a decimal
add exceeds 99, otherwise carry is reset The overflow flag is set
when the sign or bit 7 is changed due to the result exceeding +127
or -128, otherwise overflow is reset. The negative flag is set if
the accumulator result contains bit 7 on, otherwise the negative
flag is reset. The zero flag is set if the accumulator result is 0,
otherwise the zero flag is reset.
It is a "Group One" instruction and has the following address-
ing modes: Immediate; Absolute; Zero Page; Absolute,X; Absolute,Y;
Zero Page,X; indexed Indirect; and Indirect Indexed.
The ninth bit of the result is stored in the carry flag and
the remaining 8 bits reside in the accumulator. The carry flag can
be thought of as a flag bit which is remote from the accumulator it-
self but which is directly affected by accumulator operations as
though it were a ninth bit in the accumulator. The primary reason
for not viewing the carry bit as merely a ninth bit in the accumu-
lator is that one has program control over its state by being able
to set (to "1") or clear (to "0") the bit and, of course, it is not
part of the 8-bit accumulator in data transfer operations. Examples
employing the Add with Carry operation follow.
Example 2.1: Add 2 numbers with carry; no carry generation
0000 1101 13 = (A)*
1101 0011 211 = (M)*
1 1 = CARRY
Carry = /0/ 1110 0001 225 = (A)
*(A) and (M) refer to the "contents" of the accumulator and
"contents" of memory respectively.
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Example 2.2: Add 2 numbers with carry; carry generation
1111 1110 254 = (A)
0000 0110 6 = (M)
1 1 = CARRY
Carry = /1/ 0000 0101 5 = (A)
While the accumulator contains "5," the carry flag signals
the user that the result exceeded 255 and, therefore, the result can
be properly interpreted as 256 + 5 = 261.
2.2.1.0 Multiple Precision Addition
To perform the addition of 2 numbers, one issues to the
microprocessor an ADC instruction which adds the memory and the accu-
mulator and stores the results in the accumulator with the carry bit
going set if the results exceeded 255.
To add numbers which had significantly higher value than
255, it would be necessary to represent these numbers by a series of
serial 8-bit numbers. With the 16 bits in 2 serial 8-bit numbers,
it is possible to represent binary numbers of greater than 65,000 in
value. In order to add two 16-bit numbers together and thus accomplish
double precision addition, one first loads the lowest byte of one
number into the accumulator, clears the carry flag and then adds the
second number to the first number in the accumulator using the ADC
command. One would then store this result into another memory loca-
tion using the STA command. The carry flag would now represent the
carry from the lowest byte to the highest byte. One could then load
the high order byte of the first number, add with carry again to the
high value of the second number, and store the result in the high
order byte of the result. Thus, it can be seen that the carry allows
us to perform as much precision arithmetic as is necessary. The
example listing below displays the commands used to execute the addi-
tion of two 16-bit numbers.
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Example 2.3: Adding two 16-bit numbers
High Order Byte Low Order Byte
First Number H1 L1
Second Number H2 L2
Result of Addition H3 L3
LDA L1 Load low order byte, first number
CLC Clear carry flag (carry = 0)
ADC L2 Add L1 to low order byte, second number
STA L3 Store result in memory, carry flag is
still set if set in ADC operation
LDA H1 Load high order byte, first number
ADC H2 Add Hi and carry value from first ADC
operation to high order byte, second
number
STA H3 Store result in memory
In this example it was necessary to clear the carry flag
before starting the add instruction. This, of course, means that
commands exist that set and clear the carry flag allowing for addi-
tion without values generated from the prior operation. One could
also, at the end of the program, check to see if the result exceeded
16 bits by testing the carry flag. Exactly how one alters and tests
flags will be discussed in the Flag and Branches Section. The
examples below display the concept of carry from the addition of the
low order bytes.
Example 2.4: Add two 16-bit numbers, no carry from low
order add
0000 0001 0000 0010 258
0001 0000 0001 0000 4112
Add low order bytes: (clear carry)
0000 0010 (A)
0001 0000 (M)
Carry = /0/ 0001 0010 (A)
Add high order bytes (carry = 0):
0000 0001 (A)
0001 0000 (M)
0 (C)
Carry = /0/ 0001 0001 (A)
Result = 0001 0001 0001 0010 = 4370
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Example 2.5: Add two 16-bit numbers, with carry from low
order add
0000 0001 1000 0000 384
0000 0000 1000 0000 128
Add low order bytes: (clear carry)
1000 0000 (A)
1000 0000 (M)
Carry = /1/ 0000 0000 (A)
Add high order bytes: (carry = 1)
0000 0001 (A)
0000 0000 (M)
1 CARRY
Carry = /0/ 0000 0010 (A)
Result = 0000 0010 0000 0000 = 512
2.2.1.1 Signed Arithmetic
It is possible to look at the add operation and the way
data is represented in memory in a different way. If, in the 16-bit
problem (Examples 2.4 and 2.5), one were working with 15 bits of pre-
cision (in other words, 15 bits of valid data) plus 1 bit of sign (0
for positive and 1 for negative), it would be possible to perform
signed binary arithmetic without changing the adder, but by merely
changing the way the results are interpreted. In order to facili-
tate this concept, the microprocessor has the ability to represent
positive or negative numbers by means of a sign flag which will be
discussed at length in Section 3.7. In the MCS650X family, bit 7 is
the sign position bit. This means that the highest order byte in a
series of bytes should have the sign in the eighth position. If,
for simplicity, one talks about signed 8-bit numbers, it would mean
that one was allowed only 128 combinations of each sign because that
is the most that can be represented in 7 bits, with the eighth bit or
the highest bit reserved for the sign position.
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7 6 5 4 3 2 1 0 <- BIT POSITION
| | | | | | | | |
| | | | | | | | |
^ "1" = NEGATIVE
|__ SIGN POSITION
"0" = POSITIVE
Byte Orientation with Sign Position
FIGURE 2.3
In the following examples of signed arithmetic it should be
noted that operations are occurring on a 7-bit field of numbers and
that any carry generated out of that field will reside in the eighth
bit--not in the carry flag discussed during the add operations. The
generation of a carry out of the field is the same as when adding
two 8-bit numbers, except for the fact that the normal carry flag
does not correctly represent the fact that the field has been ex-
ceeded. This is because the true carry from adding the two 7-bit
numbers resides in the sign bit position. Therefore, the carry flag
has no real meaning. Instead, there is a separate flag, the over-
flow flag, used to indicate when a carry from 7 bits has occurred
and allows the user to write correction programs.
In each example, the negative numbers are in two's comple-
ment form. Also included in each result will be the status of the
carry and overflow flags. The overflow flag is set whenever the
sign bit (bit 7) is changed as a result of the operation.
Example 2.6: Add 2 positive numbers with no overflow
0000 0101 +5 (A)
0000 0111 +7 (M)
Carry = /0/ 0000 1100 +12 (A)
Overflow = /0/ "0" in bit 7 indicates positive result.
Note that both the carry and overflow
flag remain cleared.
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Example 2.7: Add 2 positive numbers with overflow
0111 1111 +127 (A)
0000 0010 + 2 (N)
Carry = /0/ 1000 0001 "-127" (A)
Overflow = /1/ "1" in bit 7 indicates negative result and
the two's complement of the result is 127;
however, the overflow flag is set indicat-
ing the allowable range was exceeded in the
addition.
Therefore, examination of the overflow indicated that the result was
in fact not negative but that the bit 7 position represented an over-
flow beyond the value of 127. Hence the user is flagged of an incor-
rect result and a correction routine (program) must follow.
Example 2.8: Add positive and negative number with posi-
tive result
0000 0101 +5 (A)
1111 1101 -3 (M)
Carry = /1/ 0000 0010 +2 (A)
Overflow = /0/ "0" in bit 7 indicates positive result.
(Recall that though the carry flag is set,
it has no meaning in signed operations.)
Example 2.9: Add positive and negative number with negative
result
0000 0101 +5 (A)
1111 1001 -7 (M)
Carry = /0/ 1111 1110 -2 (A)
Overflow = /0/ "1" in bit 7 indicates negative result.
Example 2.10: Add 2 negative numbers without overflow
1111 1011 -5 (A)
1111 1001 -7 (M)
Carry = /1/ 1111 0100 -12 (A)
Overflow = /0/ "1" in bit 7 indicates negative result.
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Example 2.11: Add 2 negative numbers with overflow
1011 1110 -66 (A)
1011 1111 -65 (M)
Carry = /1/ 0111 1101 "+125" (A)
Overflow = /1/ "0" indicates positive result, but the
overflow flag is set indicating that the
allowable range was exceeded in the opera-
tion. Without the overflow indication, the
result would be interpreted as +125. The
overflow, however, indicated that the result
was negative and exceeded the value -128.
Hence the user is flagged of an incorrect
result, indicating the need for a correc-
tion routine.
2.2.1.2 Decimal Addition
There is a way for the user to organize data for decimal
operations. The MOS Technology, Inc. MCS650X microprocessors have
a modified adder which allows the user to represent his numbers as
two 4-bit binary coded decimals (BCD) numbers packed into a single
byte. This is a unique feature of the MCS650X family in that the
operation in the following example can be performed.
Example 2.12: Decimal addition
CLC Clear Carry Flag
SED Set Decimal Mode
LDA 0111 1001 79
ADC 0001 0100 +14
STA 1001 0011 93
The microprocessor adder has the unique capability of per-
forming real time correction to the normal expected binary result
without any direct interference from the programmer. Other popular
microprocessors require a separate instruction (Decimal Adjust)
which corrects the direct binary result of the arithmetic unit to
obtain the same final results as are available on this microprocessor
directly.
In order to make the same arithmetic unit perform either as
a binary adder or as a decimal adder, the user chooses the mode in
which be is going to operate (either decimal or binary) by setting
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another flip-flop in the microprocessor called the decimal flag. As
shown in this example, one not only initializes the adder by clearing
the carry flag, but also puts the processor into decimal mode with
the SED instruction. Even though this also requires 1 instruction,
it is possible to put the machine in decimal mode once and perform
many long strings of decimal numbers without further user interven-
tion. The "Decimal Adjust" feature on other microprocessors requires
programming subsequent to each binary operation.
2.2.1.3 Add Summary
In summary, the basic arithmetic unit is a binary adder
which, under control of the ADC command, performs binary arithmetic
on the accumulator and data, storing the result in the accumulator.
Depending on the way the user looks at the data which is presented to
the adder and the results which are obtained from it, the user can
determine whether or not the result exceeds 255 binary or 99 decimal;
he can perform precision arithmetic by use of the ninth bit or carry
flag; he can control whether or not the microprocessor is a decimal
adder by setting the decimal mode; and he can represent his numbers
as signed binary numbers by analyzing other flags that are set in
the machine.
2.2.2 SBC Subtract Memory from Accumulator with Borrow
This instruction subtracts the value of memory and borrow from
the value of the accumulator, using two's complement arithmetic, and
stores the result in the accumulator. Borrow is defined as the carry
flag complemented; therefore, a resultant carry flag indicates that a
borrow has not occurred.
The symbolic representation for this instruction is
A - M - C -> A.
This instruction affects the accumulator. The carry flag is
set if the result is greater than or equal to 0. The carry flag is
reset when the result is less than 0, indicating a borrow. The over-
flow flag is set when the result exceeds +127 or -127, otherwise it
14
is reset. The negative flag is set if the result in the accumulator
has bit 7 on, otherwise it is reset. The Z flag is set if the result
in the accumulator is 0, otherwise it is reset.
It is a "Group One" instruction. It has addressing modes
Immediate; Absolute; Zero Page; Absolute,X; Absolute,Y; Zero Page,X;
Indexed Indirect; and Indirect Indexed.
In a binary machine, the classical way to perform arithmetic
is by using two's complement notation. In using two's complement
notation, any subtraction operation becomes a sequence of bit comple-
mentations and additions. This reduces the complexity of the circuits
required to perform a subtraction.
When the SBC instruction is used in single precision subtrac-
tion, there will normally be no borrow; therefore, the programmer
must set the carry flag, by using the SEC (Set carry to 1) instruc-
tion, before using the SBC instruction. The microprocessor adds the
carry flag to the complemented memory data, resulting in a true two's
complement form of the memory value with its sign inverted.
Example 2.13: Subtract 2 numbers with borrow; positive result
Assume a single precision subtraction where A contains 5 and N com-
tains 3. The carry flag must be set to a 1 using the SEC instruc-
tion, thereby representing the no-borrow condition.
The adder changes the sign of N by taking the two's complement
of M. This involves complementing N and adding the carry bit.
M = 3 0000 0011
Complemented M 1111 1100
Add C = 1 1
-M = -3 1111 1101
The adder adds A and the two's complement -N together. This
operation occurs simultaneously with the complement operation.
A = 5 0000 0101
Add -M = -3 1111 1101
Carry = /1/ 0000 0010 = +2
The presence of the carry flag after this operation indicates
that No Borrow was required, therefore the result is +2.